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Project # 20
Damage Progression study of 3D TSV package during thermal loading

Team Lead: Unique Rahangdale
Other Team Members: Sonkolon Barua | Dikshya Bhattari
Faculty Advisor(s): Dr. Dereje Agonafer
Department: MAE
Project Type: Graduate Student
Title: Damage Progression study of 3D TSV package during thermal loading
Abstract: Driven by the demand for smaller and more powerful electronic devices, 3D packaging technologies like Through-Silicon Vias (TSVs) are becoming increasingly important. However, these advanced packaging methods introduce new reliability challenges, particularly due to CTE (Coefficient of Thermal Expansion) mismatches between materials like copper and SiO2 used in TSVs. These mismatches can lead to significant thermal stresses and interfacial delamination, often driven by shear stress concentrations. This study investigates the impact of package structure on the thermomechanical reliability of 3D packages, focusing on optimizing die and substrate thickness to mitigate crack formation in TSVs and BEOL (Back End of the Line) structures. Using finite element analysis (FEA) and a compact modeling methodology in ANSYS Workbench 17.2, the research analyzes thermal stresses and fracture parameters, employing the J-integral to quantify crack driving force. By varying die and substrate thicknesses during the chip attachment process and under thermal cycling, the study identifies an optimized package structure that minimizes crack driving energy in critical regions. This optimized design effectively reduces the risk of brittle failure and improves the overall thermomechanical reliability of 3D packages, contributing to the development of more robust and durable electronic devices.
Poster: View Poster #20 (PDF)
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