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Project # 98
Edge Intelligence and FPGA-Based AI Acceleration
| Team Lead: | Kartikey Sharan |
| Other Team Members: | Thomas Anderson | Sam Trinh | Johan Lael Kapnang Ketcheuzeu |
| Faculty Advisor(s): | Bill Carroll |
| Department: | CSE |
| Project Type: | REU |
| Title: | Edge Intelligence and FPGA-Based AI Acceleration |
| Abstract: | Edge intelligence demands high-performance inference under strict energy and latency constraints. This work presents a cross-platform benchmarking study of deep neural network inference across CPU, GPU, and FPGA architectures, with a focus on deployment using an Intel Agilex 7 FPGA. Leveraging the Intel FPGA AI Suite and OpenVINO toolchain, we implement and evaluate a ResNet-50 image classification model optimized for FPGA-based acceleration. We establish a fair comparison framework by benchmarking equivalent model configurations across CPU, GPU, and FPGA platforms, measuring latency, throughput, and resource utilization. On the FPGA, the model is compiled using Intel’s DLA workflow, enabling hardware-aware optimizations tailored for edge deployment. Preliminary results demonstrate competitive throughput with significantly improved performance-per-watt compared to conventional CPU and GPU baselines, highlighting the FPGA’s advantages for energy-constrained edge environments. The poster presentation will showcase our benchmarking methodology, experimental setup, and quantitative results, along with a live demonstration of ResNet-50 inference running on the Agilex 7 development board. This work provides a foundation for future optimization through quantization and hardware–software co-design, and illustrates the growing role of reconfigurable computing in scalable, low-power AI inference at the edge. |
| Poster: | View Poster #98 (PDF) |
| Judges Scoring: | Submit Evaluation (judges only) |